The present invention relates generally to integrated circuits, and, more particularly, to a logic built-in self-test (LBIST) debug controller for an integrated circuit.
Integrated circuits (ICs) include various analog and digital components on a single chip. With advancements in semiconductor technology, more and more components are being added, which can make testing the components difficult and time consuming. Further, the number of I/O pins is limited by the overall size of the IC. Thus, many of today's ICs include internal logic provided specifically for testing the internal IC circuitry. This logic is known as logic built-in self-test (LBIST) circuitry.
An LBIST system typically is used to detect stuck-at-faults. An LBIST debug controller acts as an interface between the LBIST system and a tester, and facilitates in diagnosing any detected faults. The LBIST system includes a pseudo-random pattern generator (PRPG), scan chains, and a multiple-input shift register (MISR). The PRPG generates scan input signals. Each scan chain includes a set of flip-flops that is connected serially to the PRPG. Each scan chain receives corresponding scan input signal and generates a scan out signal. The MISR receives the scan out signals, compresses them, and generates a signature, which is compared to a signature stored in the tester. If the signatures do not match, the LBIST system determines that the IC contains a fault.
Although the LBIST system facilitates determination of whether or not the IC contains a fault, it does not help in detection of the location of the fault location. A manual fault analysis needs to be performed to locate the fault. Manual fault analysis is both difficult and time consuming. Further, this technique does not facilitate masking of faulty scan chains, and hence, does not provide an effective solution for testing ICs.
It would be advantageous to have an LBIST debug controller that facilitates determination of fault locations and can mask faulty scan chains.